The present invention relates to substrates for use in semiconductor packages, and more particularly, to a substrate for preventing warpage of the substrate.
A substrate for use as a chip carrier in a semiconductor package is generally formed with a core layer made of a resin material such as epoxy resin, polyimide resin, BT (bismaleimide triazine) resin or FR4 resin. A copper film is attached to opposing upper and lower surfaces of the core layer respectively, and subjected to exposing, developing and etching processes to pattern the copper film to form a plurality of conductive traces, each of the conductive traces having a terminal. Then, solder mask is applied over the upper and lower surfaces of the core layer to form a protective layer that covers the conductive traces but exposes the terminals of the conductive traces; this protective layer protects the conductive traces against external moisture and contaminant. The exposed terminals of the conductive traces may serve as ball pads or bond fingers to be subsequently bonded with conductive elements such as solder balls or bonding wires.
When using the above substrate in package fabrication processes, the upper and lower surfaces of the core layer usually function differently; for example, the upper surface is used to accommodate chips, and the lower surface may be implanted with a plurality of conductive elements such as solder balls to be in electrical connection externally, such that conductive traces formed on the upper surface of the core layer are arranged differently from those on the lower surface of the core layer. As a result, due to great mismatch in coefficient of thermal expansion (CTE) between copper-made conductive traces and the core layer, the substrate would warp under temperature variation. FIGS. 5A and 5B illustrate a warped substrate 1, which comprises: a core layer 10; an upper metal layer 11 formed of a plurality of copper-made conductive traces on an upper surface 12 of the core layer 10; a lower metal layer 13 formed of a plurality of copper-made conductive traces on a lower surface 14 of the core layer 10; an upper solder mask layer 15 applied over the upper metal layer 11 for covering the conductive traces; and a lower solder mask layer 16 applied over the lower metal layer 13 for covering the conductive traces.
As shown in FIG. 5A, when metal (copper) content of the upper metal layer 11 is less than that of the lower metal layer 13, under temperature variation in fabrication processes such as substrate baking, encapsulant curing and subsequent thermal cycles, the upper and lower metal layers 11, 13 generate different thermal stress in a manner that, the lower metal layer 13 deforms or shrinks to a greater extent than the upper metal layer 11, making the substrate 1 warped or bent downwardly.
As shown in FIG. 5B, if metal content of the upper metal layer 11 is greater than that of the lower metal layer 13, under temperature variation, the upper metal layer 11 would deform or shrink to a greater extent than the lower metal layer 13, making the substrate 1 warped or bent upwardly.
In order to solve the above substrate problem caused by CTE mismatch, U.S. Pat. No. 5,473,119 discloses a substrate with stress absorbing means. As shown in FIG. 6, this substrate 2 is composed of a support layer or core layer 20, a stress-relieving layer 21 and a conductive layer 22 having a plurality of conductive traces. The stress-relieving layer 21 is made of expanded polytetrafluoroethylene (PTFE) and has compressive modulus smaller than 50,000 pounds per square inch, wherein the expanded PTFE has high porosity, a very low dielectric constant and very low CTE.
When an electronic element such as semiconductor chip 23 is mounted and electrically connected to the substrate 2 via solder bumps 24, under temperature variation in subsequent fabrication processes, the stress-relieving layer 21 would absorb CTE-induced stress effect between the semiconductor chip 23 and the substrate 2 to thereby prevent cracking of the solder bumps 24, such that structural intactness and electrical connection quality can be assured.
The above substrate 2 with the stress-relieving layer 21 indeed eliminates structural damage caused by CTE mismatch. However, provision of the stress-relieving layer 21 on the support layer or core layer 20 increases thickness of the substrate 2, and is not favorable for miniaturization of package profile. Moreover, fabrication of the stress-relieving layer 21 increases production complexity and costs of the substrate 2, thereby not compliant with economic concern of package production.
A primary objective of the present invention is to provide a warpage preventing substrate, wherein traces formed on opposing surfaces of the substrate are balanced in stress generation under temperature variation, to thereby prevent warpage of the substrate and maintain flatness of the substrate, such that quality and yield of fabricated package products with the substrate can be assured.
Another objective of the invention is to provide a warpage preventing substrate, which would not increase thickness and fabrication costs of the substrate, in favor of low profile and low cost concerns for package products with the substrate.
In accordance with the above and other objectives, the present invention proposes a warpage preventing substrate, comprising: a core layer having a first surface and a second surface opposed to the first surface; a plurality of first conductive traces and second conductive traces respectively formed on the first surface and the second surface of the core layer, each of the conductive traces having a terminal; a plurality of first non-functional traces and second non-functional traces respectively formed on the first surface and the second surface of the core layer at area free of the conductive traces, wherein the first non-functional traces are arranged in different density from the second non-functional traces, so as to allow stress generated from the first conductive traces and first non-functional traces on the first surface of the core layer to counteract stress generated from the second conductive traces and second non-functional traces on the second surface of the core layer, to thereby assure flatness of the substrate; and an insulating layer applied over each of the first and second surfaces of the core layer, for covering the conductive traces and non-functional traces, with the terminals of the conductive traces being exposed to outside of the insulating layers.
When the above substrate is applied to package fabrication processes, under temperature variation in fabrication processes such as substrate baking, encapsulant curing and subsequent thermal cycles, by different-density arrangement of the first and second non-functional traces to balance contents of metal (used for making conductive and non-functional traces) deposited on the first and second surfaces of the core layer, thermal stress generated from the first conductive traces and first non-functional traces on the first surface of the core layer can counteract thermal stress generated from the second conductive traces and second non-functional traces on the second surface of the core layer, such that the substrate can be prevented from warpage and remains flat, and quality and yield of package products with the substrate can be assured. Furthermore, the first and second non-functional traces are simultaneously formed with the first and second conductive traces, which would not increase thickness and fabrication costs of the substrate in favor of low profile and low cost concerns for package products with the substrate.